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NTHD4401P
1.0
D = 0.5
0.2
0.1
0.1
0.05
Normalized to θ JA at 10s.
0.02
Chip
0.0175 Ω
0.0710 Ω
0.2706 Ω
0.5776 Ω
0.7086 Ω
0.01
SINGLE PULSE
0.0154 F
0.0854 F
0.3074 F
1.7891 F
107.55 F
Ambient
0.01
1.0E?03
1.0E?02
1.0E?01
1.0E+00
1.0E+01
1.0E+02
1.0E+03
t, TIME (s)
Figure 12. Thermal Response
SOLDERING FOOTPRINT*
0 .45 7
0.018
2 .03 2
0.08
2 .03 2
0.08
0.63 5
0.025
0 .63 5
0.025
1 .09 2
0.043
0.17 8
0.007
0.45 7
0.018
0.66
0.026
0.711
0.028
SCALE 20:1
mm
inches
0.66
0.026
0.25 4
0.010
SCALE 20:1
mm
inches
Figure 13. Basic
Figure 14. Style 2
*For additional information on our Pb?Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in
Figure 13. This is sufficient for low power dissipation
MOSFET applications, but power semiconductor
performance requires a greater copper pad area, particularly
for the drain leads.
The minimum recommended pad pattern shown in
Figure 14 improves the thermal area of the drain
confines of the basic footprint. The drain copper area is
0.0019 sq. in. (or 1.22 sq. mm). This will assist the power
dissipation path away from the device (through the copper
leadframe) and into the board and exterior chassis (if
applicable) for the single device. The addition of a further
copper area and/or the addition of vias to other board layers
will enhance the performance still further.
connections (pins 5, 6, 7, 8) while remaining within the
http://onsemi.com
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